? semiconductor components industries, llc, 2006 august, 2006 ? rev. 1 1 publication order number: NTTD2P02R2/d NTTD2P02R2 power mosfet ?2.4 amps, ?20 volts dual p ? channel micro8 features ? ultra low r ds(on) ? higher efficiency extending battery life ? logic level gate drive ? miniature micro ? 8 surface mount package ? diode exhibits high speed, soft recovery ? micro8 mounting information provided applications ? power management in portable and battery ? powered products, i.e.: cellular and cordless telephones and pcmcia cards maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit drain ? to ? source voltage v dss ? 20 v gate ? to ? source voltage ? continuous v gs 8.0 v thermal resistance ? junction ? to ? ambient (note 1.) total power dissipation @ t a = 25 c continuous drain current @ t a = 25 c continuous drain current @ t a = 70 c pulsed drain current (note 3.) r ja p d i d i d i dm 160 0.78 ? 2.4 ? 1.92 ? 20 c/w w a a a thermal resistance ? junction ? to ? ambient (note 2.) total power dissipation @ t a = 25 c continuous drain current @ t a = 25 c continuous drain current @ t a = 70 c pulsed drain current (note 3.) r ja p d i d i d i dm 88 1.42 ? 3.25 ? 2.6 ? 30 c/w w a a a operating and storage temperature range t j , t stg ? 55 to +150 c single pulse drain ? to ? source avalanche energy ? starting t j = 25 c (v dd = ? 20 vdc, v gs = ? 4.5 vdc, peak i l = ? 5.0 apk, l = 28 mh, r g = 25 ) e as 350 mj maximum lead temperature for soldering purposes for 10 seconds t l 260 c 1. minimum fr ? 4 or g ? 10 pcb, steady state. 2. mounted onto a 2 square fr ? 4 board (1 sq. 2 oz cu 0.06 thick single sided), steady state. 3. pulse test: pulse width 300 s, duty cycle 2%. micro8 case 846a style 2 be marking diagram yww d s g 1 8 device package shipping ordering information NTTD2P02R2 micro8 4000/tape & reel http://onsemi.com ? 2.4 amperes ? 20 volts r ds(on) = 90 m p ? channel y = year ww = work week be = device code source 1 1 2 3 4 8 7 6 5 top view gate 1 source 2 gate 2 drain 1 drain 1 drain 2 drain 2 pin assignment
NTTD2P02R2 http://onsemi.com 2 electrical characteristics (t c = 25 c unless otherwise noted) (note 1) characteristic symbol min typ max unit off characteristics drain ? to ? source breakdown voltage (v gs = 0 vdc, i d = ? 250 adc) temperature coefficient (positive) v (br)dss ? 20 ? ? ? 12.7 ? ? vdc mv/ c zero gate voltage drain current (v gs = 0 vdc, v ds = ? 16 vdc, t j = 25 c) (v gs = 0 vdc, v ds = ? 16 vdc, t j = 125 c) i dss ? ? ? ? ? 1.0 ? 25 adc zero gate voltage drain current (v gs = 0 vdc, v ds = ? 20 vdc, t j = 25 c) i dss ? ? ? 5.0 adc gate ? body leakage current (v gs = ? 8 vdc, v ds = 0 vdc) i gss ? ? ? 100 nadc gate ? body leakage current (v gs = +8 vdc, v ds = 0 vdc) i gss ? ? 100 nadc on characteristics gate threshold voltage (v ds = v gs , i d = ? 250 adc) temperature coefficient (negative) v gs(th) ? 0.5 ? ? 0.90 2.5 ? 1.4 ? vdc mv/ c static drain ? to ? source on ? state resistance (v gs = ? 4.5 vdc, i d = ? 2.4 adc) (v gs = ? 2.7 vdc, i d = ? 1.2 adc) (v gs = ? 2.5 vdc, i d = ? 1.2 adc) r ds(on) ? ? ? 0.070 0.100 0.110 0.090 0.130 ? forward transconductance (v ds = ? 10 vdc, i d = ? 1.2 adc) g fs 2.0 4.2 ? mhos dynamic characteristics input capacitance (v ds = ? 16 vdc, v gs = 0 vdc, f = 1.0 mhz) c iss ? 550 ? pf output capacitance c oss ? 200 ? reverse transfer capacitance c rss ? 100 ? switching characteristics (notes 2 & 3) turn ? on delay time (v dd = ? 10 vdc, i d = ? 2.4 adc, v gs = ? 4.5 vdc, r g = 6.0 ) t d(on) ? 10 ? ns rise time t r ? 31 ? turn ? off delay time t d(off) ? 33 ? fall time t f ? 29 ? turn ? on delay time (v dd = ? 10 vdc, i d = ? 1.2 adc, v gs = ? 2.7 vdc, r g = 6.0 ) t d(on) ? 15 ? ns rise time t r ? 40 ? turn ? off delay time t d(off) ? 35 ? fall time t f ? 35 ? total gate charge (v ds = ? 16 vdc, v gs = ? 4.5 vdc, i d = ? 2.4 adc) q tot ? 10 18 nc gate ? source charge q gs ? 1.5 ? gate ? drain charge q gd ? 5.0 ? body ? drain diode ratings (note 2) diode forward on ? voltage (i s = ? 2.4 adc, v gs = 0 vdc) (i s = ? 2.4 adc, v gs = 0 vdc, t j = 125 c) v sd ? ? ? 0.88 ? 0.75 ? 1.0 ? vdc reverse recovery time (i s = ? 2.4 adc, v gs = 0 vdc, di s /dt = 100 a/ s) t rr ? 37 ? ns t a ? 16 ? t b ? 21 ? reverse recovery stored charge q rr ? 0.025 ? c 1. handling precautions to protect against electrostatic discharge is mandatory. 2. indicates pulse test: pulse width = 300 s max, duty cycle = 2%. 3. switching characteristics are independent of operating junction temperature.
NTTD2P02R2 http://onsemi.com 3 v gs = ? 1.5 v v gs = ? 1.7 v v gs = ? 1.9 v t j = 55 c t j = 25 c v gs = ? 10 v v gs = ? 4.5 v v gs = ? 2.5 v figure 1. on ? region characteristics. figure 2. transfer characteristics. figure 3. on ? resistance vs. gate ? to ? source voltage. figure 4. on ? resistance vs. drain current and gate voltage. figure 5. on ? resistance variation with temperature. figure 6. drain ? to ? source leakage current vs. voltage. v gs = ? 2.1 v t j = 25 c t j = 100 c t j = 25 c t j = 25 c v gs = ? 2.7 v v gs = ? 4.5 v i d = ? 2.4 a v gs = ? 4.5 v v gs = 0 v t j = 125 c t j = 25 c t j = 100 c v ds > = 10 v 150 ? 50 1.6 1.4 ? 25 0 25 75 1.2 1 0.8 0.6 20 0 1000 100 4 8 12 16 10 1 0.1 0.01 ? v ds, drain ? to ? source voltage (volts) 125 100 50 t j, junction temperature ( c) 1 0.12 0.1 1.5 2 2.5 3.5 0.08 0.06 0.04 4.5 4 3 2 0.2 0.15 46 0.1 0.05 0 8 1 5 4 1.5 2 3 2 0 3 0 4 3 6 2 1 0 8 1 2.5 4 210 ? i d, drain current (amps) ? v ds , drain ? to ? source voltage (volts) ? v gs , gate ? to ? source voltage (volts) ? v gs, gate ? to ? source voltage (volts) ? i d, drain current (amps) ? i d, drain current (amps) ? i dss, leakage (na) r ds(on) , drain ? to ? source resistance ( ) r ds(on) , drain ? to ? source resistance ( ) r ds(on) , drain ? to ? source resistance (normalized)
NTTD2P02R2 http://onsemi.com 4 t r t, time (ns) gate ? to ? source or drain ? to ? source voltage (volts) t d (off) t d (off) figure 7. capacitance variation figure 8. gate ? to ? source and drain ? to ? source voltage versus total charge figure 9. resistive switching time variation versus gate resistance figure 10. resistive switching time variation versus gate resistance figure 11. diode forward voltage versus current figure 12. diode reverse recovery waveform v ds = 0 v v gs = 0 v t j = 25 c c iss c rss c oss c iss c rss v dd = ? 10 v i d = ? 1.2 a v gs = ? 2.7 v t f t d (on) t r t f v gs = 0 v t j = 25 c di/dt t rr t a t p i s 0.25 i s time i s t b 1 0 0.9 0.8 0.7 0.6 0.5 0.4 0.4 0.8 1.2 1.6 2 ? v sd, source ? to ? drain voltage (volts) 1.0 100 10 1.0 10 100 10 100 10 1.0 100 1000 r g, gate resistance (ohms) 20 10 1500 1200 5051015 900 600 300 0 r g, gate resistance (ohms) t, time (ns) ? i s, source current (amps) v dd = ? 10 v i d = ? 2.4 a v gs = ? 4.5 v t d (on) c, capacitance (pf) ? v ds ? v gs qt q2 q1 v gs i d = ? 2.4 a t j = 25 c v ds 0 8 0 3 5 1 4 246 10 14 q g , total gate charge (nc) 20 18 16 14 12 10 8 6 4 2 0 ? v ds, drain ? to ? source voltage (volts) 12 2 ? v gs, gate ? to ? source voltage (volts)
NTTD2P02R2 http://onsemi.com 5 0.1 figure 13. fet thermal response. normalized to r ? ja at steady state (1 inch pad) 0.0125 0.0563 0.110 0.273 0.113 0.436 0.021 f 0.137 f 1.15 f 2.93 f 152 f 261 f 0.01 0.02 0.05 0.2 single pulse d = 0.5 r thja(t), effective transient thermal response t, time (s) 1e ? 03 1e ? 02 1e ? 01 1e+00 1e+03 1e+02 1e+03 1 0.1 0.01 information for using the micro ? 8 surface mount package minimum recommended footprint for surface mounted applications surface mount board layout is a critical portion of the total design. the footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. with the correct pad geometry, the packages will self ? align when subjected to a solder reflow process. mm inches 0.041 1.04 0.208 5.28 0.015 0.38 0.0256 0.65 0.126 3.20
NTTD2P02R2 http://onsemi.com 6 soldering precautions the melting temperature of solder is higher than the rated temperature of the device. when the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. ? always preheat the device. ? the delta temperature between the preheat and soldering should be 100 c or less.* ? when preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. when using infrared heating with the reflow soldering method, the difference shall be a maximum of 10 c. ? the soldering temperature and time shall not exceed 260 c for more than 10 seconds. ? when shifting from preheating to soldering, the maximum temperature gradient shall be 5 c or less. ? after soldering has been completed, the device should be allowed to cool naturally for at least three minutes. gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. ? mechanical stress or shock should not be applied during cooling. * * soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. typical solder heating profile for any given circuit board, there will be a group of control settings that will give the desired heat pattern. the operator must set temperatures for several heating zones and a figure for belt speed. taken together, these control settings make up a heating ?profile? for that particular circuit board. on machines controlled by a computer, the computer remembers these profiles from one operating session to the next. figure 14 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. this profile will vary among soldering systems, but it is a good starting point. factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. this profile shows temperature versus time. the line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. the two profiles are based on a high density and a low density board. the vitronics smd310 convection/infrared reflow soldering system was used to generate this profile. the type of solder used was 62/36/2 tin lead silver with a melting point between 177 ? 189 c. when this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. the components on the board are then heated by conduction. the circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. step 1 preheat zone 1 ?ramp? step 2 vent ?soak? step 3 heating zones 2 & 5 ?ramp? step 4 heating zones 3 & 6 ?soak? step 5 heating zones 4 & 7 ?spike? step 6 vent step 7 cooling 200 c 150 c 100 c 5 c time (3 to 7 minutes total) t max solder is liquid for 40 to 80 seconds (depending on mass of assembly) 205 to 219 c peak at solder joint desired curve for low mass assemblies desired curve for high mass assemblies 100 c 150 c 160 c 170 c 140 c figure 14. typical solder heating profile
NTTD2P02R2 http://onsemi.com 7 tape & reel information micro ? 8 dimensions are shown in millimeters (inches) feed direction section a ? a notes: 1. conforms to eia ? 481 ? 1. 2. controlling dimension: millimeter. pin number 1 notes: 1. conforms to eia ? 481 ? 1. 2. controlling dimension: millimeter. 3. includes flange distortion at outer edge. 4. dimension measured at inner hub. 12.30 4.10 (.161) 11.70 (.484) (.461) 1.85 (.072) 3.90 (.154) 2.05 (.080) 1.95 (.077) bba a 8.10 (.318) 7.90 (.312) 5.55 (.218) 5.45 (.215) 1.65 (.065) 1.60 (.063) 1.50 (.059) 1.60 (.063) 1.50 (.059) typ. 0.35 (.013) 0.25 (.010) 3.50 (.137) 3.30 (.130) 1.50 (.059) 1.30 (.052) section b ? b 5.40 (.212) 5.20 (.205) 330.0 (13.20) max. 50.0 (1.97) min. 14.4 (.57) 12.4 (.49) note 4 18.4 (.724) max. note 3 13.2 (.52) 12.8 (.50)
NTTD2P02R2 http://onsemi.com 8 package dimensions style 2: pin 1. source 1 2. gate 1 3. source 2 4. gate 2 5. drain 2 6. drain 2 7. drain 1 8. drain 1 s b m 0.08 (0.003) a s t dim min max min max inches millimeters a 2.90 3.10 0.114 0.122 b 2.90 3.10 0.114 0.122 c ??? 1.10 ??? 0.043 d 0.25 0.40 0.010 0.016 g 0.65 bsc 0.026 bsc h 0.05 0.15 0.002 0.006 j 0.13 0.23 0.005 0.009 k 4.75 5.05 0.187 0.199 l 0.40 0.70 0.016 0.028 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. ? b ? ? a ? d k g pin 1 id 8 pl 0.038 (0.0015) ? t ? seating plane c h j l micro8 case 846a ? 02 issue e on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NTTD2P02R2/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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